/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright (C) 2021 Renesas Electronics Corp.
 */
#ifndef __DT_BINDINGS_CLOCK_R9A07G043U_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R9A07G043U_CPG_MSSR_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* r9a07g043u CPG Core Clocks */
#define R9A07G043U_CLK_I		0
#define R9A07G043U_CLK_I2		1
#define R9A07G043U_CLK_G		2
#define R9A07G043U_CLK_S0		3
#define R9A07G043U_CLK_S1		4
#define R9A07G043U_CLK_SPI0		5
#define R9A07G043U_CLK_SPI1		6
#define R9A07G043U_CLK_SD0		7
#define R9A07G043U_CLK_SD1		8
#define R9A07G043U_CLK_M0		9
#define R9A07G043U_CLK_M1		10
#define R9A07G043U_CLK_M2		11
#define R9A07G043U_CLK_M3		12
#define R9A07G043U_CLK_M4		13
#define R9A07G043U_CLK_HP		14
#define R9A07G043U_CLK_TSU		15
#define R9A07G043U_CLK_ZT		16
#define R9A07G043U_CLK_P0		17
#define R9A07G043U_CLK_P1		18
#define R9A07G043U_CLK_P2		19
#define R9A07G043U_CLK_AT		20
#define R9A07G043U_OSCCLK		21

/* r9a07g043u Module Clocks */

#define R9A07G043U_CLK_GIC600		0
#define R9A07G043U_CLK_IA55		1
#define R9A07G043U_CLK_SYC		2
#define R9A07G043U_CLK_DMAC		3
#define R9A07G043U_CLK_SYSC		4
#define R9A07G043U_CLK_MTU		5
#define R9A07G043U_CLK_ETH0		6
#define R9A07G043U_CLK_ETH1		7
#define R9A07G043U_CLK_I2C0		8
#define R9A07G043U_CLK_I2C1		9
#define R9A07G043U_CLK_I2C2		10
#define R9A07G043U_CLK_I2C3		11
#define R9A07G043U_CLK_SCIF0		12
#define R9A07G043U_CLK_SCIF1		13
#define R9A07G043U_CLK_SCIF2		14
#define R9A07G043U_CLK_SCIF3		15
#define R9A07G043U_CLK_SCIF4		16
#define R9A07G043U_CLK_SCI0		17
#define R9A07G043U_CLK_SCI1		18
#define R9A07G043U_CLK_GPIO		19
#define R9A07G043U_CLK_SDHI0		20
#define R9A07G043U_CLK_SDHI1		21
#define R9A07G043U_CLK_USB0		22
#define R9A07G043U_CLK_USB1		23
#define R9A07G043U_CLK_CANFD		24
#define R9A07G043U_CLK_SSI0		25
#define R9A07G043U_CLK_SSI1		26
#define R9A07G043U_CLK_SSI2		27
#define R9A07G043U_CLK_SSI3		28
#define R9A07G043U_CLK_MHU		29
#define R9A07G043U_CLK_OSTM0		30
#define R9A07G043U_CLK_OSTM1		31
#define R9A07G043U_CLK_OSTM2		32
#define R9A07G043U_CLK_WDT0		33
#define R9A07G043U_CLK_WDT2		34
#define R9A07G043U_CLK_WDT_PON		35
#define R9A07G043U_CLK_ISU		36
#define R9A07G043U_CLK_CRU		37
#define R9A07G043U_CLK_LCDC		38
#define R9A07G043U_CLK_SRC		39
#define R9A07G043U_CLK_RSPI0		40
#define R9A07G043U_CLK_RSPI1		41
#define R9A07G043U_CLK_RSPI2		42
#define R9A07G043U_CLK_ADC		43
#define R9A07G043U_CLK_TSU_PCLK		44
#define R9A07G043U_CLK_SPI		45
#define R9A07G043U_CLK_CSI2		46

#endif /* __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__ */
